MPC8540 datasheet(806/1302 Pages) FREESCALE

806 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-28

Freescale Semiconductor

DMA Controller

15.4 Functional Description

This section describes the function of the the DMA controller.

15.4.1 DMA Channel Operation

All DMA channels support two different modes of operation; a basic mode (MRn[XFE] is cleared)

and an extended mode (MRn[XFE] is set). In both modes, a channel can be activated by clearing

and setting MRn[CS], or via the single-write start mode using MRn[CDSM/SWSM] and

MRn[SRW], or via an external control mode using MRn[ECS_EN].

In basic mode, the channel can be programmed in basic direct mode or basic chaining mode. In

extended mode, the channel can be programmed in extended direct mode or extended chaining

mode. Extended mode provides more capabilities, such as extended descriptor chaining, striding

capabilities, and a more flexible descriptor structure.

TE2

Transfer error, Channel 2

0 Normal operation

1 An error condition occurred during the DMA transfer.

—

Reserved

CH2

Channel halted, Channel 2

PE2

Programming error, Channel 2

EOLNI2

End-of-links interrupt, Channel 2

CB2

Channel busy, Channel 2

EOSI2

End-of-segment interrupt, Channel 2

EOLSI2

End-of-lists/direct interrupt, Channel 2

TE3

Transfer error, Channel 3

0 Normal operation

1 An error condition occurred during the DMA transfer.

—

Reserved

CH3

Channel halted, Channel 3

PE3

Programming error, Channel 3

EOLNI3

End-of-links interrupt, Channel 3

CB3

Channel busy, Channel 3

EOSI3

End-of-segment interrupt, Channel 3

EOLSI3

End-of-lists/direct interrupt, Channel 3

Table 15-20. DGSR Field Descriptions (continued)

Bits

Name

Description

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