MPC8540 datasheet(810/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-32

Freescale Semiconductor

DMA Controller

5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.

6. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the

last descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1),

or if an error occurs during any of the transfers.

15.4.1.2 Extended DMA Mode Transfer

The extended DMA mode also operates in chaining and direct mode. It offers additional capability

over the basic mode by supporting striding and a more flexible descriptor structure. This additional

functionality also requires a new and more complex programming model. The extended DMA

mode is activated by setting MRn[XFE].

15.4.1.2.1 Extended Direct Mode

Extended direct mode has the same functionality as basic direct mode with the addition of stride

capabilities. The bit settings are the same as in direct mode with the exception of the MRn[XFE]

being set. Striding on the source address can be accomplished by setting SATRn[SSME] and

setting the desired stride size and distance in SSRn. Striding on the destination address can be

accomplished by setting DATRn[DSME] and setting the desired stride size and distance in DSRn.

15.4.1.2.2 Extended Direct Single-Write Start Mode

Extended direct single-write start mode has the same functionality as the basic direct single-write

start mode with the addition of stride capabilities. The bit settings are also the same with the

exception of MRn[XFE] being set. Striding on the source address can be accomplished by setting

SATRn[SSME] and setting the desired stride size and distance in SSRn. Striding on the destination

address can be accomplished by setting DATRn[DSME] and setting the desired stride size and

distance in DSRn.

15.4.1.2.3 Extended Chaining Mode

In extended chaining mode, the software must first build list and link descriptor segments in

memory. Then CLSDARn must be initialized to point to the first list descriptor in memory. The

DMA controller loads list descriptors and link descriptors from memory prior to a DMA transfer.

The DMA controller begins the transfer according to the link descriptor information loaded. Once

the current link descriptor is finished, the DMA controller reads the next link descriptor from

memory and begins another DMA transfer. If the current link descriptor is the last in the list, the

DMA controller reads the next list descriptor in memory. The transfer is finished if the current link

descriptor is the last one in the last list in memory or if an error condition occurs. The sequence of

events to start and complete a transfer in extended chaining mode is as follows:

1. Build link and list descriptor segments in memory. See Section 15.4.4, “DMA

Descriptors,” for more information on descriptors.

MPC8540 Datasheet(PDF) 810 Page - Freescale Semiconductor, Inc