MPC8540 datasheet(813/1302 Pages) FREESCALE

813 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-35

If CC is set by software while the channel is busy with a transfer, the DMA controller finishes all

transfers until it reaches the EOLND in basic mode or EOLSD in extended mode. The DMA

controller then refetches the last link descriptor in basic mode, or the last list descriptor in extended

mode and clears the channel continue bit. If EOLND or EOLSD is still set for their respective

modes, the DMA controller remains in the idle state. If EOLND or EOLSD is not set, the DMA

controller continues the transfer by refetching the new descriptor.

If CC is set by software while the channel is not busy with a transfer, the DMA controller refetches

the last link descriptor in basic mode, or the last list descriptor in extended mode and clears the

channel continue bit. If EOLND or EOLSD is still set for their respective modes, the DMA

controller remains in the idle state. If the EOLND or EOLSD bits are not set, the DMA controller

continues the transfer by refetching the new descriptor.

15.4.1.4.1 Basic Mode

On a channel continue, the descriptor at the current link descriptor address register (CLNDARn)

is refetched to get the next link descriptor address field as updated by software. The channel halts

if NLNDARn[EOLND] is still set. If EOLND is zero, the next link descriptor address is copied

into CLNDARn and the channel continues with another descriptor fetch of the current link

descriptor address. As a result, two link descriptor fetches always exist after channel continue

before starting the first transfer.

15.4.1.4.2 Extended Mode

On a channel continue, the descriptor at the current list descriptor (CLSDARn) address register is

refetched to get the next list descriptor address field as updated by software. The channel halts if

NLSDARn[EOLSD] is still set. If not, the next list descriptor address is copied into the CLSDARn

address. As a result, two list descriptor fetches always exist after channel continue before the first

link descriptor fetch and the first transfer.

15.4.1.5 Channel Abort

Software can abort a previously initiated transfer by setting MRn[CA]. Once the DMA channel

controller detects a zero-to-one transition of MRn[CA], it finishes the current sub-block transfer

and halts all further activity. The controller then waits for all previously initiated transfers from the

specified channel to drain and clears SRn[CB]. Successful completion of a software initiated abort

request can be recognized by MRn[CA] being set and SRn[CB] being cleared. Obviously, if the

controller was already halted because of an error condition (SRn[TE] is set), or the channel has

completed all transfers, then SRn[CB] being cleared may not signify that the controller entered a

halt state due to the abort request.

MPC8540 Datasheet(PDF) 813 Page - Freescale Semiconductor, Inc