MPC8540 datasheet(811/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-33

2. Poll the channel state (see Table 15-21), to confirm that the specific DMA channel is idle.

3. Initialize CLSDARn to point to the first list descriptor in memory.

4. Clear the mode register channel transfer mode bit, MRn[CTM], to indicate chaining mode.

MRn[XFE] must be set to indicate extended DMA mode. Other control parameters may

also be initialized in the mode register.

5. Clear, then set the mode register channel start bit, MRn[CS], to start the DMA transfer.

6. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.

7. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the

last descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1),

or if an error occurs during any of the transfers.

15.4.1.2.4 Extended Chaining Single-Write Start Mode

In the extended mode, the single-write start feature allows a chain to be started by writing the

current list descriptor pointer. Setting MRn[CDSM/SWSM] causes MRn[CS] to be set

automatically when CLSDARn is written. The sequence of events to start and complete an

extended chain using single-write start mode is as follows:

1. Set MRn[CDSM/SWSM], MRn[CTM], and MRn[XFE] to indicate extended chaining and

single-write start mode. Also other control parameters may be initialized in the mode

2. Build list and link descriptor segments in local memory.

3. Poll the channel state (see Table 15-21), to confirm that the specific DMA channel is idle.

4. Initialize the current list descriptor address register to point to the first list descriptor

segment in memory. This write automatically causes the DMA controller to begin the list

descriptor fetch and set MRn[CS].

5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.

6. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the

last descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1),

or if an error occurs during any of the transfers.

15.4.1.3 External Control Mode Transfer

An external control can be used to control all DMA channels by setting MRn[EMS_EN]. The

external control can control the DMA channel in the following transfer modes:

•

Basic direct

•

Basic chaining

•

Extended direct

•

Extended chaining

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