MPC8540 datasheet(808/1302 Pages) FREESCALE

808 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-30

Freescale Semiconductor

DMA Controller

byte count register have been transferred or if an error condition occurs. The sequence of events

to start and complete a transfer in basic direct mode is as follows:

1. Poll the channel state (see Table 15-21), to confirm that the specific DMA channel is idle.

2. Initialize SARn, SATRn, DARn, DATRn and BCRn.

3. Set the mode register channel transfer mode bit, MRn[CTM], to indicate direct mode.

Other control parameters may also be initialized in the mode register.

4. Clear then set the mode register channel start bit, MRn[CS], to start the DMA transfer.

5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.

6. SRn[CB] is automatically cleared by the DMA controller after the transfer is finished, or if

the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if a transfer error occurs.

7. End of segment interrupt is generated if MRn[EOSIE] is set.

15.4.1.1.2 Basic Direct Single-Write Start Mode

In basic direct single-write start mode, the DMA controller does not read descriptors from

memory, but instead uses the current parameters programmed in the DMA registers to start the

DMA transfer. Software is responsible for initializing the SATRn, DATRn, and BCRn registers.

Setting MRn[SRW] configures the DMA controller to begin the DMA transfer either when SARn

is written or when DARn is written, determined by the state of MRn[CDSM/SWSM]. Writing to

SARn initiates the DMA transfer if MRn[CDSM/SWSM] is set. Writing to DARn initiates the

DMA transfer if MRn[CDSM/SWSM] is cleared. The DMA controller automatically sets the

channel start bit, MRn[CS]. Software is expected to program all the appropriate registers before

writing the source or destination address registers. The transfer is finished after all the bytes

specified in the byte count register have been transferred or if an error condition occurs. The

sequence of events to start and complete a transfer in single-write start basic direct mode is as

follows:

1. Poll the channel state (see Table 15-21), to confirm that the specific DMA channel is idle.

2. Initialize the source attributes (SATRn), DATRn, and BCRn registers.

3. Set the mode register channel transfer mode bit, MRn[CTM], and the single-write start

direct mode bit, MRn[SRW]. Other control parameters may also be initialized in the mode

MRn[CDSM/SWSM] for transfers started using the DARn.

4. A write to the source or destination address register starts the DMA transfer and

automatically sets MRn[CS].

5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.

6. SRn[CB] is automatically cleared by the DMA controller after the transfer is finished, or if

the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if a transfer error occurs.

7. End of segment interrupt is generated if MRn[EOSIE] is set.

MPC8540 Datasheet(PDF) 808 Page - Freescale Semiconductor, Inc