MPC8540 datasheet(812/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-34

Freescale Semiconductor

DMA Controller

The external control and the DMA controller use a well defined protocol to communicate. The

external control can start or pause a DMA transfer. The DMA controller acknowledges a DMA

transfer in progress and also indicates a transfer completion.

The pause feature can be enabled by setting MRn[EMP_EN]. MRn[BWC] specifies how much

data to allow a specific channel to transfer before entering a paused state by clearing MRn[CS].

The channel can be restarted from a paused state by the external master. In chaining modes, the

channel does not pause for descriptor fetch transfer. It only pauses during the actual data transfer.

The following signals are defined for the external control interface:

•

DMA_DREQ, Indicates a DMA transfer start or restart from a pause request. The falling

edge of DMA_DREQ sets MRn[CS].

•

DMA_DACK, Indicates a DMA transfer currently in progress. SRn[CB] is set.

•

DMA_DDONE, Indicates that the DMA engine has completed the transfer. SRn[CB] is

clear. Note, however, that write data may still be queued at the target interface or in the

process of transfer on an external interface.

Detailed descriptions of the external control interface are in Table 15-4. The timing diagram of the

external control interface is shown in Figure 15-22.

Figure 15-22. External Control Interface Timing

15.4.1.4 Channel Continue Mode for Cascading Transfer Chains

The channel continue mode (enabled when MRn[CC] is set) offers software the flexibility of

having the DMA controller get started on descriptors that have already been programmed while

software continues to build more descriptors in memory. Software can set the end-of-links

descriptor (EOLND) in basic mode, or end-of-lists descriptor (EOLSD) in extended mode, to

cause the channel to go into a halted state while software continues to build other descriptors in

memory. Software can then set CC to force hardware to continue where it left off. Channel

continue is only meaningful for chaining modes, not direct mode.

DREQ

CLOCK

DACK

DDONE

Transfer Start

Transfer In Progress

Transfer Done

Transfer Start

Transfer Pause

Transfer Restart

EMP_EN

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