MPC8540 datasheet(816/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-38

Freescale Semiconductor

DMA Controller

NOTE

Software must ensure that each descriptor is aligned on a 32-byte

boundary.

The last link descriptor in the last list in memory sets NLNDARn[EOLND] in the next link

descriptor and NLSDARn[EOLSD] in the next list descriptor fields indicating that these are the

last descriptors in memory. Software initializes the current list descriptor address register to point

to the first list descriptor in memory. The DMA controller traverses through the descriptor lists

until the last link descriptor is met as shown in Figure 15-24. For each link descriptor in the chain,

the DMA controller starts a new DMA transfer with the control parameters specified by that

descriptor. Table 15-22 summarizes the DMA list descriptors.

Table 15-23 summarizes the DMA link descriptors.

Table 15-22. DMA List Descriptor Summary

Descriptor Field

Description

Next list descriptor

address

Points to the next list descriptor in memory. After the DMA controller reads the descriptor from

memory, this field is loaded into the next list descriptor address registers.

First link descriptor

address

Points to the first link descriptor in memory for this list. After the DMA controller reads the descriptor

from memory, this field is loaded into the current link descriptor address registers.

Source stride

Contains the stride information used for the data source if striding is enabled for a link in the list.

Destination stride

Contains the stride information used for the data destination if striding is enabled for a link in the list.

Table 15-23. DMA List Descriptor Summary

Descriptor Field

Description

Source attributes register

Contains source transaction attributes.

Source address

Contains the source address of the DMA transfer. After the DMA controller reads the

descriptor from memory, this field is loaded into the Source address register.

Destination attributes register

Contains destination transaction attributes.

Destination address

Contains the destination address of the DMA transfer. After the DMA controller reads the

descriptor from memory, this field is loaded into the destination address register.

Next link descriptor address

Points to the next link descriptor in memory. After the DMA controller reads the link

descriptor from memory, this field is loaded into the next link descriptor address

registers.

Byte count

Contains the number of bytes to transfer. After the DMA controller reads the descriptor

from memory, this field is loaded into the byte count register.

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