MPC8540 datasheet(819/1302 Pages) FREESCALE

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DMA System Considerations

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-41

The DMA controller restrictions are as follows:

•

Setting the source or destination priority level (STFLOWLVL or DTFLOWLVL) to a value

of three (0b11) is considered a programming error.

•

All interface capabilities from where descriptors are being fetched must support read sizes

32-bytes or greater.

•

If MRn[SAHE] is set, the source interface transfer size capability must be greater than or

equal to MRn[SAHTS]. The source address must be aligned to the size specified by

SAHTS.

•

If MRn[DAHE] is set, the destination interface transfer size capability must be greater than

or equal to MRn[DAHTS]. The destination address must be aligned to the size specified by

DAHTS.

•

Destination striding is not supported if MRn[DAHE] is set and source striding is not

supported if MRn[SAHE] is set.

•

If the DMA is programmed to send SWRITEs over RapidIO, the programmer must ensure

that the destination address is double-word aligned and that the byte count is a double-word

multiple.

•

If the DMA is programmed to send messages over RapidIO, the programmer must ensure

that the message length (BCRn[BC]) is 8, 16, 32, 64, 128 or 256 bytes. This can be achieved

by setting the byte count register (BCR) to a power of 2 value equal to 8 or greater.

•

Striding does not work if the destination transaction type is MESSAGE

(DATR[DWRITETTYPE] = 0x0110) because messages have no memory addresses. As

well, destination address hold should be disabled (MRn[DAHE] is cleared) unless the

destination address hold transfer size indicates an 8-byte message (MRn[DAHTS] = 0x11).

Software is responsible for disabling striding and DAHE, in this case, and for ensuring that

the bandwidth control is large enough to support the desired message size. Failure to adhere

to these restrictions results in boundedly undefined behavior.

•

When DMA is used to issue maintenance reads and writes in bypass mode, the sum of the

starting offset field in DAR and the byte count must not cause the offset to rollover. Failure

to adhere to this restriction results in boundedly undefined behavior.

15.5 DMA System Considerations

Figure 15-27 shows the most important data paths within the MPC8540. Many of these paths are

served by captive DMA controllers and virtually all can be served by the general purpose

four-channel DMA controller. This section provides information about how to make most

effective use of these DMA channels including the following topics:

•

DMA transaction initiators (masters)

•

DMA targets, that is, data sources and destinations

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