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MPC8540 Datasheet(PDF) 821 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 821 Page - Freescale Semiconductor, Inc

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DMA System Considerations
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
15-43
transfers; rather, they operate transparently with respect to both on- and off-chip DMA controllers.
The codes in the table cells have the following meaning:
•
Y—Supported
•
NR—Possible, but not recommended. Inefficient use of system resources.
•
NS—Possible, but not supported. Resulting system behavior is not defined.
15.5.1 Unusual DMA Scenarios
The following is a description of unusual DMA paths including explanations of why some
functional blocks cannot serve as DMA targets. The following topics are addressed:
•
Transaction initiators (masters)
•
DMA targets, that is, data sources or destinations
•
Transparency of the bus controllers to DMA transactions
•
What is useful as opposed to what is possible. For example, any register can be addressed
through an internal control bus, which means configuration and control registers can be
DMA targets.
15.5.1.1 DMA to e500 Core
The L1 cache cannot be a direct DMA target because it cannot be directly addressed by software.
However, DMA access into the L1 cache occurs indirectly if a block of memory that is cached in
the L1 is specified as the DMA target. This effect is deterministic if the target memory block was
locked into the L1 with cache locking instructions.
Table 15-24. DMA Paths
DMA
Controllers
On-Chip Targets
Off-Chip Targets
L2
Configuration
Registers1
1 Includes I2C data register.
DDR
Local
Bus
PCI/
PCI-X
RapidIO
DUART
FIFO
Ethernet
Buffers
On-chip
Ethernet2
2 Captive resource. Not available to external masters.
YNS
Y
Y
Y
Y
Y
Y
4 Channel3
3 Can serve external masters.
YNR
Y
Y
Y
Y
Y
NS
Off-chip
PCI-X Controller
YNS
Y
Y
—
Y
Y
Y
RapidIO Controller
YNS
Y
Y
Y
—
Y
Y



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