MPC8540 datasheet(824/1302 Pages) FREESCALE

824 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-2

Freescale Semiconductor

PCI/PCI-X Bus Interface

Figure 16-1. PCI/X Controller Block Diagram

16.1.1 Overview

The PCI/X controller connects the OCeaN to the PCI/X bus, to which I/O components are

connected. The PCI bus uses a 32- or 64-bit multiplexed address/data bus, plus various control and

error signals. The PCI/X interface supports address and data parity with error checking and

reporting.

The PCI/X interface of the MPC8540 functions both as a master (initiator) and a target device.

Internally, the design is divided into the following:

•

Data path blocks

•

Control logic blocks

•

Memory

The data path blocks contain the queues, tables for transaction tracking, and ordering. The control

blocks contain control logic and state-machines for buffer control, bus protocol, tag generation,

and transaction resizing. The memory blocks are used solely for inbound and outbound data

storage.

This allows the MPC8540 to handle separate PCI/X transactions simultaneously. For example,

consider the case where a burst-write transaction from the MPC8540 to another PCI device

OCeaN Physical Interface

PCI/X Interface

Fabric

Request

Data Out

Data In

Arb

PCI

PCI-X

Regs

Interface

MPC8540 Datasheet(PDF) 824 Page - Freescale Semiconductor, Inc