MPC8540 datasheet(828/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-6

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.1.3.1.1 Host Mode

When the device powers up in host mode, all inbound configuration accesses are ignored (and thus

master aborted). See Section 16.5.1.1, “Host Mode,” for more information.

16.1.3.1.2 Agent Mode

When the device powers up in agent mode, it acknowledges inbound configuration accesses. See

Section 16.5.1.2, “Agent Mode,” for more information. Note that in PCI agent mode, the PCI/X

controller ignores all PCI/X memory accesses except those to the memory-mapped registers) until

inbound address translation is enabled.

16.1.3.1.3 Agent Configuration Lock Mode

When the device powers up in agent configuration lock mode, it retries inbound configuration

accesses until the ACL bit in the PCI bus function register is cleared. See Section 16.5.1.3, “Agent

Configuration Lock Mode,” for more information.

16.1.3.2 PCI/X Bus Width (64-/32-Bit Bus)

This input configures the PCI/X interface to be in 32-bit or 64-bit extended mode of operation. The

initial value is determined by the value on the PCI_REQ64 power-on reset configuration signal.

See Chapter 4, “Reset, Clocking, and Initialization,” and the MPC8540 Integrated Processor

Hardware Specifications, for more information.

16.1.3.3 PCI/X Arbiter (Internal/External Arbiter)

This input configures the on-chip PCI/X arbiter. The initial value is determined by the value on the

PCI_GNT2 power-on reset configuration signal. See Chapter 4, “Reset, Clocking, and

Initialization,” and the MPC8540 Integrated Processor Hardware Specifications.

16.1.3.4 PCI/X Bus Mode

This input configures PCI or PCI-X mode on the PCI/X port. Note that this input does not support

the three states of the PCIXCAP input defined in the PCI-X specification. It is sampled as either

a 1 or a 0 during reset only. The initial value is determined by the value on the PCI_GNT4

power-on reset configuration signal. See Chapter 4, “Reset, Clocking, and Initialization,” and the

MPC8540 Integrated Processor Hardware Specifications.

16.1.3.5 PCI/X Signal Output Hold Timing

To meet minimum output hold specifications relative to SYSCLK for both PCI and PCI-X

systems, the MPC8540 has a programmable output hold delay for bus signals. The initial value of

the output hold delay is determined by the values on the LWE[0:1] power-on reset configuration

MPC8540 Datasheet(PDF) 828 Page - Freescale Semiconductor, Inc