MPC8540 datasheet(830/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-8

Freescale Semiconductor

PCI/PCI-X Bus Interface

Table 16-2 contains the detailed descriptions of the external PCI/X interface signals.

Table 16-2. PCI Interface Signals—Detailed Signal Descriptions

Signal

Description

PCI_ACK64

64-bit transaction acknowledge.Indicates that the current target supports 64-bit transfers during the

data phase of the current transaction.

O As an output for the bidirectional 64-bit transaction acknowledge, this signal operates as follows:

State

Meanin

Asserted—Indicates that this PCI controller, as the target of a PCI transaction, may use

the full 64-bit data bus for the data phase of the transaction.

Negated—Indicates that this PCI controller, as the target of a PCI transaction, may use

only 32 bits of the data bus in servicing a data transfer.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As an input for the bidirectional 64-bit transaction acknowledge, this signal operates as follows:

State

Meanin

Asserted—Indicates that the target of a PCI transaction may use the full 64-bit data bus

for the data phase of the transaction.

Negated—Indicates that the target of a PCI transaction may only use 32 bits of the data

bus during the data phase of the transaction.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_AD[63:0]

PCI address/data bus

O As outputs for the bidirectional PCI address/data bus, these signals operate as described below.

State

Meanin

Asserted/Negated—Represents the physical address during the address phase of a PCI

transaction. During the data phase(s) of a PCI transaction, the PCI address/data

bus contain the data being written.

The PCI_AD[7:0] signals define the LSB and PCI_AD[63:56] define the MSB.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional PCI address/data bus, these signals operate as described below.

State

Meanin

Asserted/Negated—Represents the address to be decoded as a check for device select

during the address phase of a PCI transaction or the data being received during the

data phase(s) of a PCI transaction.

The PCI_AD[7:0] signals define the LSB and PCI_AD[63:56] define the MSB.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

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