MPC8540 datasheet(833/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-11

PCI_IRDY

Initiator ready

O As outputs for the bidirectional initiator ready, these signals operate as described below.

State

Meanin

Asserted—Indicates that this PCI controller, acting as a PCI master, can complete the

current data phase of a PCI transaction. During a write, this PCI controller asserts

PCI_IRDY to indicate that valid data is present on PCI_AD[63:0]. During a read,

this PCI controller asserts PCI_IRDY to indicate that it is prepared to accept data.

Negated—Indicates that the PCI target needs to wait before this PCI controller, acting as

a PCI master, can complete the current data phase. During a write, this PCI

controller negates PCI_IRDY to insert a wait cycle when it cannot provide valid data

to the target. During a read, this PCI controller negates PCI_IRDY to insert a wait

cycle when it cannot accept data from the target.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional initiator ready, these signals operate as described below.

State

Meanin

Asserted—Indicates another PCI master can complete the current data phase of a

transaction.

Negated—If PCI_FRAME is asserted, indicates a wait cycle from another master. If

PCI_FRAME is negated, indicates the PCI bus is idle.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_PAR

PCI parity.

O As outputs for the bidirectional PCI parity, these signals operate as described below.

State

Meanin

Asserted—Indicates odd parity across PCI_AD[31:0] and PCI_C/BE[3:0] during address

and data phases.

Negated—Indicates even parity across PCI_AD[31:0] and PCI_C/BE[3:0] during

address and data phases.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional PCI parity, these signals operate as described below.

State

Meanin

Asserted—Indicates odd parity driven by another PCI master or the PCI target during

read data phases.

Negated—Indicates even parity driven by another PCI master or the PCI target during

read data phases.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)

Signal

Description

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