MPC8540 datasheet(835/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-13

PCI_REQ[4:0]

PCI bus request

. Input signals on this PCI controller when the arbiter is enabled. When the arbiter

is disabled, PCI_REQ[0] is an output. Note that PCI_REQ[n] is a point-to-point signal. Every master

has its own bus request signal. Following is the state meaning for the PCI_REQ[n] input.

State

Meanin

Asserted—Indicates that agent n is requesting control of the PCI bus to perform a

transaction.

Negated—Indicates that agent n does not require use of the PCI bus.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_REQ64

64-bit transaction request. Indicates that the current master desires to transfer data using 64-bit

transfers. Also used as a reset configuration signal in the MPC8540 as described in Section 4.4.3,

“Power-On Reset Configuration.”

O As an output for the bidirectional 64-bit transaction request, this signal operates as follows:

State

Meanin

Asserted—Indicates that this PCI controller, as the master of a PCI transaction, desires

to use all 64 bits.

Negated—Indicates that this PCI controller, as the master of a PCI transaction, uses only

32 bits of the data bus in servicing a data transfer.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As an input for the bidirectional 64-bit transaction request, this signal operates as described below.

State

Meanin

Asserted—Indicates that the master of a PCI transaction is requesting to use the full

64-bit data bus for the data phase of the transaction.

Negated—Indicates that the master of a PCI transaction uses only 32 bits of the data bus

during the data phase of the transaction.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_SERR

PCI system error

O As outputs for the bidirectional PCI system error, these signals operate as described below.

State

Meanin

Asserted—Indicates that an address parity error, a target-abort (when this PCI controller

is acting as the initiator), or some other system error (where the result is a

catastrophic error) was detected.

Negated—Indicates no error.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional PCI system error, these signals operate as described below.

State

Meanin

Asserted—Indicates that a target (other than this PCI controller) has detected a

catastrophic error.

Negated—Indicates no error.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)

Signal

Description

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