MPC8540 datasheet(832/1302 Pages) FREESCALE

832 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-10

Freescale Semiconductor

PCI/PCI-X Bus Interface

PCI_FRAME

Frame

O As outputs for the bidirectional frame, these signals operate as described below.

State

Meanin

Asserted—Indicates that this PCI controller, acting as a PCI master, is initiating a bus

transaction. While PCI_FRAME is asserted, data transfers may continue.

Negated—If PCI_IRDY is asserted, indicates that the PCI transaction is in the final data

phase; if PCI_IRDY is negated, indicates that the PCI bus is idle.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional frame, these signals operate as described below.

State

Meanin

Asserted—Indicates that another PCI master is initiating a bus transaction.

Negated—Indicates that the transaction is in the final data phase or that the bus is idle.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_GNT[4:0]

O PCI bus grant. Output signals on this PCI controller when the arbiter is enabled. When the arbiter

is disabled, PCI_GNT0 is an input. Note that PCI_GNT[n] is a point-to-point signal. Every master

has its own bus grant signal. Also, note that these signals are also used as reset configuration

signals in the MPC8540 as described in Section 4.4.3, “Power-On Reset Configuration."

State

Meanin

Asserted—Indicates that this PCI controller granted control of the PCI bus to agent n.

Negated—Indicates that this PCI controller did not grant control of the PCI bus to agent

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_IDSEL

Initialization device select. Used as a chip select during configuration read and write transactions.

State

Meanin

Asserted—Indicates this PCI controller is being selected as a target of a configuration

read or write transactions.

Negated—Indicates this PCI controller is not being selected as a target of configuration

read or write transactions.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)

Signal

Description

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