MPC8540 datasheet(836/1302 Pages) FREESCALE

836 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-14

Freescale Semiconductor

PCI/PCI-X Bus Interface

PCI_STOP

Stop.

O As outputs for the bidirectional stop, these signals operate as described below.

State

Meanin

Asserted—Indicates that this PCI controller, acting as a PCI target, is requesting that the

initiator stop the current transaction.

Negated—Indicates that the current transaction can continue.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional stop, these signals operate as described below.

State

Meanin

Asserted—Indicates that a target is requesting that the PCI initiator stop the current

transaction.

Negated—Indicates that the current transaction can continue.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

PCI_TRDY

Target ready.

O As outputs for the bidirectional target ready, these signals operate as described below.

State

Meanin

Asserted—Indicates that this PCI controller, acting as a PCI target, can complete the

current data phase of a PCI transaction. During a read, this PCI controller asserts

PCI_TRDY to indicate that valid data is present on PCI_AD[31:0]. During a write,

this PCI controller asserts PCI_TRDY to indicate that it is prepared to accept data.

Negated—Indicates that the PCI initiator needs to wait before this PCI controller, acting

as a PCI target, can complete the current data phase. During a read, this PCI

controller negates PCI_TRDY to insert a wait cycle when it cannot provide valid

data to the initiator. During a write, this PCI controller negates PCI_TRDY to insert

a wait cycle when it cannot accept data from the initiator.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

As inputs for the bidirectional target ready, these signals operate as described below.

State

Meanin

Asserted—Another PCI target is able to complete the current data phase of a

transaction.

Negated—Indicates a wait cycle from another target.

Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2 or by PCI-X

Addendum Rev 1.0a

Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)

Signal

Description

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