MPC8540 datasheet(840/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-18

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.3.1.1 PCI/X Configuration Access Registers

The PCI/X configuration header, shown in Figure 16-25 and Figure 16-26, is accessed through an

indirect method using a pair of 32-bit memory-mapped access registers, CFG_ADDR at offset

0x0_8000 and CFG_DATA at offset 0x0_8004.

16.3.1.1.1 PCI/X Configuration Address Register (CFG_ADDR)

The CFG_ADDR register is shown in Figure 16-3.

Figure 16-3. PCI/X CFG_ADDR Register

0x0_8E00

ERR_DR—PCI/X error detect register

Special

0x0000_0000

16.3.1.4.1/16-29

0x0_8E04

ERR_CAP_DR—PCI/X error capture disabled register

R/W

0x0000_0000

16.3.1.4.2/16-30

0x0_8E08

ERR_EN—PCI/X error enable register

R/W

0x0000_0000

16.3.1.4.3/16-31

0x0_8E0C

ERR_ATTRIB—PCI/X error attributes capture register

R/W

0x0000_0000

16.3.1.4.4/16-32

0x0_8E10

ERR_ADDR—PCI/X error address capture register

R/W

0x0000_0000

16.3.1.4.5/16-33

0x0_8E14

ERR_EXT_ADDR—PCI/X error extended address capture

R/W

0x0000_0000

16.3.1.4.6/16-34

0x0_8E18

ERR_DL—PCI/X error data low capture register

R/W

0x0000_0000

16.3.1.4.7/16-34

0x0_8E1C

ERR_DH—PCI/X error data high capture register

R/W

0x0000_0000

16.3.1.4.8/16-34

0x0_8E20

GAS_TIMR—PCI/X gasket timer register

R/W

0x0000_0000

16.3.1.4.9/16-35

0x0_8E24

PCIX_TIMR—PCI-X split completion timer register

R/W

0x0000_0000

16.3.1.4.10/16-3

0x0_8E28–

0x0_8EFC

Reserved

—

0x0_8F00–

0x0_8FFC

Reserved for debug

—

1516

20 21

23 24

293031

0000

Bus Number

Device

Number

Function

Number

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8000

Table 16-3. PCI/X Memory-Mapped Register Map (continued)

Offset

Access

Reset

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