MPC8540 datasheet(844/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-22

Freescale Semiconductor

PCI/PCI-X Bus Interface

Table 16-8 describes the fields of the POTEARn.

16.3.1.2.3 PCI/X Outbound Window Base Address Registers (POWBARn)

The PCI/X outbound window base address registers (POWBARn), shown in Figure 16-8, point to

the beginning of each translation window in the local 32-bit address space. Addresses for outbound

transactions are compared to the appropriate bits in these registers, according to the sizes of the

windows. If a transaction does not fall within one of these windows, the default translation and

mapping is used. The default window is always enabled and used when the other windows miss.

Note that POWBAR0 (for outbound ATMU window 0) is not used, because window 0 is the

default window used when no other windows match. POWBAR0 may be read from and written

to, but the value is ignored.

Figure 16-8. PCI/X Outbound Window Base Address Registers

Table 16-9 describes the field of the POWBARn.

16.3.1.2.4 PCI/X Outbound Window Attributes Registers (POWARn)

The PCI/X outbound window attributes registers (POWARn) define the window sizes to translate

and other attributes for the translations. The minimum window size is 4 Kbytes. The maximum

window size is 4 Gbytes.

Table 16-8. POTEARn Field Descriptions

Bits

Name

Description

0–11

—

Reserved

12–31

TEA

Translation extended address. Represents bits [63–44] of a 64-bit PCI address (used in

conjunction with POTARn)

011 12

—WBA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8C08, 0x0_8C28, 0x0_8C48, 0x0_8C68, 0x0_8C88

Table 16-9. POWBARn Field Descriptions

Bits

Name

Description

0–11

—

Reserved, should be cleared.

12–3

WBA Window base address. Source address that is the starting point for the outbound translation window.

The window must be aligned based on the size selected in the window size bits.

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