MPC8540 datasheet(847/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-25

Registers.” All accesses to PCSRBAR have an automatic internal byte lane redirection from the

little-endian PCI bus to the big-endian CCSRBAR configuration space.

16.3.1.3.1 PCI/X Inbound Translation Address Registers (PITARn)

The PCI/X inbound translation address registers (PITARn) points to the beginning of the local

address space for the inbound window. The translated address is created by concatenating the

transaction offset to this translation address. The format of the PITARn is shown in Figure 16-11.

Figure 16-11. PCI/X Inbound Translation Address Registers

Table 16-11 describes the fields of the PITARn registers.

16.3.1.3.2 PCI/X Inbound Window Base Address Registers (PIWBARn)

PCI/X inbound window base address registers (PIWBARn), shown in Figure 16-12, select the

PCI/X base address for windows translated to the MPC8540 local address space. Inbound

transaction addresses are compared to these windows. If a PCI/X transaction does not fall in one

of these spaces, the PCI/X interface does not assert DEVSEL.

Figure 16-12. PCI/X Inbound Window Base Address Registers

011

—TA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8DA0, 0x0_8DC0, 0x0_8DE0

Table 16-11. PITARn Field Descriptions

Bits

Nam

Description

0–11

—

Reserved, should be cleared.

12–3

Translation address. Indicates the starting point of the inbound translated address. The translation

address must be aligned based on the size field. TA corresponds to the high-order 20 bits of a 32-bit

local address.

011

BEA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8DA8, 0x0_8DC8, 0x0_8DE8

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