MPC8540 datasheet(850/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-28

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.3.1.4 PCI/X Error Management Registers

When a PCI/X error is detected, the appropriate error bit is set in the PCI/X error detect register.

Subsequent errors set the appropriate error bits in the error detection registers, but relevant

information (attributes, address, and data) is captured only for the first error. The PCI/X error

detect register is a write-1-to-clear type register. That is, reading from this register occurs

normally; however, write operations are different in that the bits can be cleared but not set. A bit

is cleared whenever the register is written, and the data in the corresponding bit location is a 1. For

example, to clear bit 25 and not affect any other bits in the register, the value 0x0000_0040 is

written to the register.

The error bit is set regardless of the state of the corresponding error enable bit in the PCI/X error

enable register. The error enable bits are used to send or block the error reporting to the interrupt

mechanism. The interrupt can be cleared by writing 0xFFFF_FFFF to the PCI/X error detect

Note that some errors are reported in two bits—one in the PCI/X error detect register (ERR_DR)

and another in the PCI bus status register in the PCI/X configuration header. These bits must be

cleared separately; that is, clearing one does not clear the other. For example, clearing the

16–19

WTT

Write transaction type. Transaction type to run if access is a write. The field description differs subject to

the transaction being targeted to an I/O interface or to local memory.

Following are the transaction type settings for writes to the RapidIO interface:

0000–0011 Reserved

0100 Write

0101–1111 Reserved

Following are the transaction type settings for writes to local memory:

0000–0011 Reserved

0100 Write, don’t snoop local processor

0101 Write, snoop local processor

0110 Write, allocate L2 cache line

0111 Write, allocate and lock L2 cache line

1000–1111 Reserved

20–25

—

Reserved

26–31

IWS

Inbound window size. Inbound translation window size N which is the encoded 2^(N+1) bytes window

size. The smallest window is 4 Kbytes.

000000–001010 Reserved

001011 4-Kbyte window size

001100 8-Kbyte window size

...

011111 4-Gbyte window size

100000–111111 Reserved

For configuration and run-time registers, the window size is fixed at

010011 1-Mbyte window size

For register set 0, the window size is limited to 4 Gbytes or smaller.

Table 16-14. PIWARn Field Descriptions (continued)

Bits

Name

Description

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