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MPC8540 Datasheet(PDF) 853 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 853 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definitions
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-31
16.3.1.4.3 PCI/X Error Enable Register (ERR_EN)
Figure 16-17. PCI/X Error Enable Register (ERR_EN)
Table 16-17 describes ERR_DR fields. Note that uncorrectable read errors may cause the assertion
of core_fault_in, which causes the core to generate a machine check interrupt unless it is disabled
by clearing HID1[RFXE]. If RFXE is zero and this error occurs, the appropriate parity detect and
master-abort bits in ERR_DR must be cleared and the appropriate ERR_EN bits must be set to
ensure that an interrupt is generated. See Section 6.10.2, “Hardware Implementation-Dependent
Register 1 (HID1).”
Table 16-16. ERR_CAP_DR Field Descriptions
Bits
Name
Description
0–20
—
Reserved
21
Addr parity error capture disable Disable capture for address parity errors
22
Rcvd SERR error capture
disable
Disable capture for received SERR errors
23
Mstr PERR error capture disable Disable capture for master PERR errors
24
Trgt PERR error capture disable Disable capture for target PERR errors
25
Mstr abort error capture disable
Disable capture for master-abort errors
26
Trgt abort error capture disable
Disable capture for target abort errors
27
OWMSV error capture disable
Disable capture for outbound write memory space violation errors
28
ORMSV error capture disable
Disable capture for outbound read memory space violation errors
29
IRMSV error capture disable
Disable capture for PCI/X inbound read memory space violation errors
30
SCM error capture disable
Disable capture for PCI/X split completion message errors
31
TOE error capture disable
Disable capture for PCI/X time out errors
0
20
2122
2324
25
26
27
28
29
30
31
R
Addr
parity
error
enable
Rcvd
SERR
error
enable
Mstr
PERR
error
enable
Trgt
PERR
error
enable
Mstr
abort
error
enable
Trgt
abort
error
enable
OWMSV
error
enable
ORMSV
error
enable
IRMSV
error
enable
SCM
error
enable
TOE
error
enable
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x0_8E08



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