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MPC8540 Datasheet(PDF) 854 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 854 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
16-32
Freescale Semiconductor
PCI/PCI-X Bus Interface
16.3.1.4.4 PCI/X Error Attributes Capture Register (ERR_ATTRIB)
Figure 16-18. PCI/X Error Attributes Capture Register (ERR_ATTRIB)
Table 16-17. ERR_EN Field Descriptions
Bits
Name
Description
0–20
—
Reserved
21
Addr parity error enable
Enable reporting address parity errors
22
Rcvd SERR error enable
Enable reporting received SERR errors
23
Mstr PERR error enable
Enable reporting master PERR errors
24
Trgt PERR error enable
Enable reporting target PERR errors
25
Mstr abort error enable
Enable reporting master-abort errors
26
Trgt abort error enable
Enable reporting target abort errors
27
OWMSV error enable
Enable reporting outbound write memory space violation errors
28
ORMSV error enable
Enable reporting outbound read memory space violation errors
29
IRMSV error enable
Enable reporting PCI/X inbound read memory space violation errors
30
SCM error enable
Enable reporting PCI/X split completion message errors
31
TOE error enable
Enable reporting PCI/X time out errors
0
3
4
7
8
9
10
11
15
16
19
20
30
31
R
High word
byte enables
Low word
byte enables
High
parity bit
Low
parity bit
Error source
Command
Valid
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x0_8E0C
Table 16-18. ERR_ATTRIB Field Descriptions
Bits
Name
Description
0–3
High word byte enables PCI byte enables for most significant word of the double word
4–7
Low word byte enables
PCI byte enables for least significant word of the double word
8
High parity bit
Parity bit for most significant PCI bus data word (only valid for 64-bit PCI bus)
9
Low parity bit
Parity bit for least significant PCI bus data word
10
—
Reserved



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