MPC8540 datasheet(851/1302 Pages) FREESCALE

851 / 1302 page

Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-29

ERR_DR[Mstr abort error] does not clear the received master abort bit in the PCI bus status

Table 16-57 for PCI mode error actions and Table 16-65 for PCI-X mode error actions. Likewise,

some errors are enabled by programming two bits—one in the PCI/X error enable register and

another in the PCI bus command register in the PCI/X configuration header.

A master-abort condition during a configuration cycle is not necessarily an error. In this case, if

relevant, the master-abort error enable can be disabled to prevent the reporting of master-aborts

during outbound configuration cycles. Master-aborts during configuration reads return

0xFFFF_FFFF.

If a data parity error occurs during an inbound configuration write access, the error is reported and

captured. However, the erroneous data is written to the register specified in the transaction.

Therefore, PCI data parity error recovery routines must include reinitialization of the PCI/X

configuration register if the error occurred during a configuration write.

A dual address cycle (DAC) transaction on the PCI bus has two address phases. The command of

the first phase is DAC and the command of the second phase is the actual transaction type. If an

error occurs on a DAC transaction, the DAC command is stored in command field in the PCI/X

error attribute capture register.

In PCI-X mode, the MPC8540 does not check the parity on the data of a split response to an

outbound read transaction because no data is actually transferred. However, outbound writes that

end with a split response do transfer data and thus parity is checked for these transactions. Also

note that the MPC8540 does drive the correct parity for inbound read transactions that it terminates

with a split response.

See Section 16.4.2.13, “PCI Error Functions,” and Section 16.4.3.8, “PCI-X Error Functions,” for

more details on error handling.

16.3.1.4.1 PCI/X Error Detect Register (ERR_DR)

Figure 16-15. PCI/X Error Detect Register (ERR_DR)

Table 16-15 describes ERR_DR fields. Note that uncorrectable read errors may cause the assertion

of core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled

(by clearing HID1[RFXE]). If RFXE is zero and an error occurs, the appropriate parity detect and

master-abort bits in ERR_DR must be cleared and the appropriate enable bits in ERR_EN must be

R Multiple

PCI

errors

Addr

Parity

error

Rcvd

SERR

error

Mstr

PERR

error

Trgt

PERR

error

Mstr

abort

error

Trgt

abort

error

OWMSV

error

ORMSV

error

IRMSV

error

SCM

error

TOE

error

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8E00

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