MPC8540 datasheet(848/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-26

Freescale Semiconductor

PCI/PCI-X Bus Interface

Table 16-12 describes the fields of the PIWBARn registers.

16.3.1.3.3 PCI/X Inbound Window Base Extended Address Registers

(PIWBEARn)

The PCI/X inbound window base extended address registers (PIWBEARn), shown in

Figure 16-13, contain the msbs of a 64-bit base address. Note that inbound window 1 supports only

a 32-bit base address and does not define an inbound window base extended address register.

Figure 16-13. PCI/X Inbound Window Base Extended Address Registers

Table 16-13 describes the fields of the PIWBEARn registers.

16.3.1.3.4 PCI/X Inbound Window Attributes Registers (PIWARn)

The PCI/X inbound window attributes registers (PIWARn) define the window sizes to translate

and other attributes for the translations. 16 Gbytes is the largest window size allowed. The format

of the PIWBARn is shown in Figure 16-14.

Table 16-12. PIWBARn Field Descriptions

Bits

Name

Description

0–11

BEA

Base extended address. Corresponds to bits 43–32 of a 64-bit PCI base address.

12–31

Base address. Corresponds to bits 31–12 of a PCI base address.

011 12

R 0

BEA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8DAC, 0x0_8DCC

Table 16-13. PIWBEARn Field Descriptions

Bits

Name

Description

0–11

—

Reserved

12–31

BEA

Base extended address. Corresponds to bits 63–44 of a 64-bit PCI base address.

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