MPC8540 datasheet(845/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-23

The default window attribute register, POWAR0, is shown in Figure 16-9. Note that the fields for

all of the POWARn registers are the same, only the reset values are different.

POWAR1–POWAR4 are shown in Figure 16-10.

Figure 16-10. PCI/X Outbound Window Attributes Registers 1–4

Table 16-10 describes the fields for the POWARn registers.

11 12

15 16

19 20

25 26

EN1

0 0 0 0000 0 0 0 0

RTT

WTT

000000

OWS

Reset

1000_0000_0000_0100_0100_0000_0001_1111 2

Offset

0x0_8C10

1 For POWAR0, translation is always enabled. The enable field (EN) may be read and written, but the value is

ignored.

2 The default window is enabled, configured for memory read and memory write, and set to an OWS size of 4

Gbytes.

Figure 16-9. PCI/X Outbound Window Attributes Register 0 (Default)

11 12

15 16

19 20

25 26

00 000 00 000 0

RTT

WTT

000000

OWS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8C30, 0x0_8C50, 0x0_8C70, 0x0_8C90

Table 16-10. POWARn Field Descriptions

Bits

Name

Description

Enable. Enables this address translation. Note that for POWAR0, translation is always enabled. The

enable field (EN) may be read and written, but the value is ignored.

1–11

—

Reserved

12–15

RTT

Read transaction type to run on PCI

0000–0011Reserved

0100 Memory Read

0101–0111Reserved

1000 I/O Read

1001–1111Reserved

16–19

WTT

Writetransaction type to run on PCI

0000–0011Reserved

0100 Memory Write

0101–0111Reserved

1000 I/O Write

1001–1111Reserved

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