MPC8540 datasheet(841/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-19

Table 16-4 describes the bit settings for the CFG_ADDR register.

Bus number 0xb00 and device number 0b0_0000 are used to configure the internal PCI/X

configuration header of the MPC8540 itself.

See Section 16.4.2.11.2, “Accessing the PCI Configuration Space in Host Mode,” and

Section 16.4.2.11.3, “PCI Configuration in Agent and Agent Lock Modes,” for usage of PCI/X

CFG_ADDR.

16.3.1.1.2 PCI/X Configuration Data Register (CFG_DATA)

The CFG_DATA register is shown in Figure 16-3.

Figure 16-4. PCI/X CFG_DATA Register

Table 16-5 describes the bit settings for the CFG_DATA register

The CFG_DATA register is a 4-byte window into the little-endian PCI/X configuration header data

structure; therefore byte addressing within the CFG_DATA register uses little-endian convention.

Note that CFG_DATA may contain 1, 2, 3, or 4 bytes depending on the size of the register being

accessed.

Table 16-4. PCI/X CFG_ADDR Field Descriptions

Bits

Name

Description

Enable

Allow a PCI configuration access when PCI CFG_DATA is accessed

1–7

—

Reserved

8–15

Bus Number

PCI bus number to access

16–20

Device Number

Device number to access on specified bus

21–23

Function Number

Function to access within specified device

24–29

32-bit register to access within specified device

30–31

—

Reserved, hardwired to logic 00

Data

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8004

Table 16-5. PCI/X CFG_DATA Field Descriptions

Bits

Name

Description

0–31

Data

A read or write to this register starts a PCI configuration cycle if the PCI CFG_ADDR

enable bit is set. If the enable bit is not set, a PCI I/O transaction is generated.

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