MPC8540 datasheet(849/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-27

Figure 16-14. PCI/X Inbound Window Attributes Registers

Table 16-14 describes the fields of the PIWARn registers.

11 12

15 16

19 20

25 26

TGI

RTT

WTT

000

IWS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8DB0, 0x0_8DD0, 0x0_8DF0

Table 16-14. PIWARn Field Descriptions

Bits

Name

Description

Enable. Enables this address translation

1—

Reserved

Prefetchable. Indicates that the address space is prefetchable so that prefetching and streaming are

attempted.

0 Not prefetchable

1 Prefetchable

3–7

—

Reserved

8–11

TGI

Target Interface.

0000–1011 Reserved

1100 RapidIO

1101–1110 Reserved

1111 Local Memory (DDR SDRAM, Local Bus, SRAM)

Note: If this field is set to an I/O port rather than local memory space, attributes for the external I/O

transaction are assigned in an outbound ATMU of that I/O controller.

12–15

RTT

Read transaction type. Transaction type to run if access is a read. The field description differs subject to

the transaction being targeted to I/O interface or to local memory.

Following are the transaction type settings for reads to the RapidIO interface:

0000–0011 Reserved

0100 Read

0101–1111 Reserved

Following are the transaction type settings for reads to local memory:

0000–0011 Reserved

0100 Read, don’t snoop local processor

0101 Read, snoop local processor

0110 Reserved

0111 Read, unlock L2 cache line

1000–1111 Reserved

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