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MPC8540 Datasheet(PDF) 852 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 852 Page - Freescale Semiconductor, Inc |
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852 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 16-30 Freescale Semiconductor PCI/PCI-X Bus Interface set to ensure that an interrupt is generated. See Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).” 16.3.1.4.2 PCI/X Error Capture Disable Register (ERR_CAP_DR) Figure 16-16. PCI/X Error Capture Disable Register (ERR_CAP_DR) Table 16-15. ERR_DR Field Descriptions Bits Name Description 0 Multiple PCI errors 0 Multiple PCI errors of the same type were not detected (write-1-to-clear) 1 Multiple PCI errors of the same type were detected 1–20 — Reserved 21 Addr Parity error Address parity error (write-1-to-clear) 22 Rcvd SERR error Received SERR error (write-1-to-clear) 23 Mstr PERR error Master PERR error (write-1-to-clear) 24 Trgt PERR error Target PERR error (write-1-to-clear) 25 Mstr abort error Master-abort error (write-1-to-clear) 26 Trgt abort error Target abort error (write-1-to-clear) 27 OWMSV error Outbound write memory space violation error (write-1-to-clear) 28 ORMSV error Outbound read memory space violation error (write-1-to-clear) 29 IRMSV error PCI/X inbound read memory space violation error (write-1-to-clear) 30 SCM error PCI/X split completion message error (write-1-to-clear) 31 TOE error PCI/X time out error (write-1-to-clear) 020 21 31 R Addr parity error capture disable Rcvd SERR error capture disable Mstr PERR error capture disable Trgt PERR error capture disable Mstr abort error capture disable Trgt abort error capture disable OWMSV error capture disable ORMSV error capture disable IRMSV error capture disable SCM error capture disable TOE error capture disable W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0x0_8E04 |
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