MPC8540 datasheet(855/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-33

16.3.1.4.5 PCI/X Error Address Capture Register (ERR_ADDR)

Figure 16-19. PCI/X Error Address Capture Register (ERR_ADDR)

11–15 Error source

The source of the PCI transaction

00000 PCI/X interface

00001 Reserved

00010–00011 Reserved

00100 Local bus controller

00101–01000 Reserved

01001 Reserved

01010–01011 Reserved

01100 RapidIO interface

01101 Reserved

01110 Reserved

01111 Reserved

10000 e500 core (instruction)

10001 e500 core (data)

10010 Reserved

10011 Reserved

10100 Reserved

10101 DMA

10110 RDC

10111 SAP

11000 TSEC1

11001 TSEC2

11010 FEC (10/100)

11011 Reserved

11100 RapidIO message units

11101 RapidIO doorbell units

11110 RapidIO port-write units

11111 Reserved

16–19 Command

PCI command

20–30 —

Reserved

Valid info

The PCI bus capture registers contain valid information

Memory Address

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_8E10

Table 16-19. ERR_ADDR Field Descriptions

Bits

Name

Description

0–31

Memory address

Memory transaction address

Table 16-18. ERR_ATTRIB Field Descriptions (continued)

Bits

Name

Description

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