MPC8540 datasheet(859/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-37

Figure 16-25. MPC8540 PCI/X Configuration Header

Figure 16-26 lists the additional PCI-X configuration registers.

Figure 16-26. PCI-X Additional Configuration Registers

Note that software must be restricted from accessing any reserved or undefined register space on

the MPC8540; doing so may hang the device.

Table 16-54 in Section 16.4.2.11.1, “PCI Configuration Space Header,” provides a summary of

the PCI configuration header registers. Detailed descriptions of these registers are provided in the

PCI Local Bus Specification.

16.3.2.1 PCI Vendor ID Register—Offset 0x00

The PCI vendor ID register, shown in Figure 16-27, is used to identify the manufacturer of the part.

Reserved

Device ID

Vendor ID

PCI Bus Status

PCI Bus Command

Bus Base Class Code

Bus Programming Interface

Subclass Code

Revision ID

BIST Control

Bus Latency Timer

Header Type

Bus Cache Line Size

PCI Bus MAX_LAT

PCI Bus Interrupt Pin

PCI Bus MIN_GNT

PCI Bus Interrupt Line

PCI Configuration and Status Register Base Address Register (PCSRBAR)

PCI Bus Arbiter Configuration

64-Bit High Memory Base Address Register

Subsystem ID

Subsystem Vendor ID

32-Bit Memory Base Address Register

64-Bit Low Memory Base Address Register

64-Bit High Memory Base Address Register

64-Bit Low Memory Base Address Register

PCI Bus Function

PCI Bus Capability Pointer

Address

Offset (Hex)

Reserved

PCI-X Command

PCI-X Status

PCI-X Next Capability

PCI-X Capability ID

Address

Offset (Hex)

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