MPC8540 datasheet(862/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-40

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.3.2.4 PCI Bus Status Register—Offset 0x06

The 2-byte PCI bus status register is used to record status information for PCI bus bus-related

events. The definition of each bit is given in Table 16-28. Only 2-byte accesses to address offset

0x06 are allowed.

Note that some errors are reported in two bits—one in the PCI bus status register and another in

the PCI/X error detect register (ERR_DR). These bits must be cleared separately; that is, clearing

one does not clear the other. For example, clearing the ERR_DR[Mstr abort error] does not clear

the received master abort bit in the PCI bus status register. In these cases, both bits must be cleared

before further error reporting can occur. Refer to Table 16-57 for PCI mode error actions and

Table 16-65 for PCI-X mode error actions. Likewise, some errors are enabled by programming

two bits—one in the PCI bus command register and another in the PCI/X error enable register

(ERR_EN).

Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but

not set. A bit is cleared whenever the register is written, and the data in the corresponding bit

location is a 1. For example, to clear bit 14 and not affect any other bits in the register, write the

value 0b0100_0000_0000_0000 to the register.

Figure 16-30. PCI Bus Status Register

Detected

parity

error

Signaled

system

error

Received

master

abort

Received

target

abort

Signaled

target

abort

DEVSEL

timing

Master

data

parity

error

detected

Fast

back-to-

back

capable

66-MHz

capable

Capabilities

list

Reset

0000_0000_1011_0000

Offset

0x06

Table 16-28. PCI Bus Status Register Field Descriptions

Bits

Name

Description

Detected parity

error

Set whenever this PCI controller detects a PCI parity error, even if parity error handling is

disabled (as controlled by bit 6 in the PCI bus command register)

Signaled system

error

Set whenever this PCI controller asserts PCI_SERR.

Received

master-abort

Set whenever this PCI controller, acting as the PCI master, terminates a transaction (except

for a special-cycle) using master-abort

Received

target-abort

Set whenever a PCI transaction initiated by this PCI controller (excluding a special-cycle) is

terminated by a target-abort

Signaled

target-abort

Set whenever this PCI controller, acting as the PCI target, issues a target-abort to a PCI

master

10–

DEVSEL timing

Hard-wired to 0b00, indicating that this PCI controller uses fast device select timing.

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