MPC8540 datasheet(866/1302 Pages) FREESCALE

866 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-44

Freescale Semiconductor

PCI/PCI-X Bus Interface

1-Mbyte window that is automatically translated to the local configuration, control, and status

registers address space.

The other base address registers are aliases (with differing format) of the PCI inbound ATMU

windows; see Section 16.3.1.3, “PCI/X ATMU Inbound Registers.” The 32-bit base address

at offsets 0x18 and 0x20 correspond to inbound ATMU windows 2 and 3. If one of these registers

is written, the corresponding ATMU register is also updated; if a PCI inbound ATMU register is

written, the corresponding BAR is also updated. If one of these registers is read, the corresponding

size of ATMU is returned on the PCI bus providing valid window size in the Inbound ATMU

window attributes register.

Note that PCSRBAR cannot be updated through the inbound ATMU registers.

Figure 16-37. PCI Configuration and Status Register Base Address Register (PCSRBAR)

Figure 16-38. 32–Bit Memory Base Address Register

20 19

ADDRESS

PREF TYPE MSI

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x10

Table 16-35. PCSRBAR Field Descriptions

Bits

Name

Description

31–2

ADDRES

Indicates the base address at which the inbound configuration/run-time window resides. This

window is fixed at 1 Mbyte.

19–4

—

Reserved

PREF

Prefetchable

2–1

TYPE

Type. 00—Locate anywhere in 32-bit address space.

MSI

Memory space indicator

12 11

ADDRESS

PREF TYPE MSI

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x14

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