MPC8540 datasheet(869/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-47

Figure 16-42. PCI Subsystem ID Register

16.3.2.14 PCI Bus Capabilities Pointer Register

The PCI bus capabilities pointer identifies additional functionality supported by the device. This

field is set to point to the PCI-X configuration registers. The definition of each bit is given in

Table 16-41.

Figure 16-43. PCI Bus Capabilities Pointer Register

16.3.2.15 PCI Bus Interrupt Line Register

Figure 16-44. PCI Bus Interrupt Line Register

Subsystem ID

Reset

0000_0000_0000_0000

Offset

0x2E

Table 16-40. PCI Subsystem ID Register Field Description

Bits

Name

Description

15–0

Subsystem ID

0x0000

Capabilities Pointer

Reset

0110_0000

Offset

0x34

Table 16-41. PCI Bus Capabilities Pointer Register Field Description

Bits

Name

Description

7–0

Capabilities

Pointer

Specifies the byte offset in the configuration space containing the first item in the capabilities

list. The default value points to the PCI-X configuration registers.

Interrupt Line

Reset

0000_0000

Offset

0x3C

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