MPC8540 datasheet(872/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-50

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.3.2.20 PCI Bus Arbiter Configuration Register (PBACR)

The PCI bus arbiter configuration register is used to determine the configuration of the PCI bus

arbiter.

Figure 16-49. PCI Bus Arbiter Configuration Register

P64

PCI 64-bit configuration. Read-only. Indicates the reset value of the PCI 64-bit configuration signal,

PCI_REQ64.

0 64-bit interface functions as a 32-bit interface.

1 64-bit interface functions as a 64-bit interface.

2–1

—

Reserved

PAH

PCI agent/host. Read-only. Indicates the reset value of the PCI host/agent configuration signal, LWE3.

0 PCI interface is in host mode

1 PCI interface is in agent mode

RPAD

PBMD

PBMP

Reset

0000_0000_0000_0000

Offset

0x46

Table 16-47. PCI Bus Arbiter Configuration Register Field Descriptions

Bits

Name

Description

PAD

PCI arbiter disable. Determines if the device is the PCI arbiter on the PCI bus or not. The reset state is

determined by the inverse of the PCI_GNT2 configuration input signal when reset is released.

0 Device is the PCI arbiter.

1 Device is not the PCI arbiter. Device presents its request on PCI_REQ0 to the external arbiter and

receives its grant on PCI_GNT0.

Parking mode. controls which device receives the bus grant when there are no outstanding bus requests

and the bus is idle.

0 The bus is parked on the last device to use the bus.

1 The bus is parked on this device.

—

Reserved

PBMD

PCI broken master disable. Determines if the device ignores the bus requests of an initiator that requests

the bus for an excessive period without using the bus.

0 An initiator that requests the bus and receives the grant must begin using the bus within 16 PCI clock

periods after the bus becomes idle or else its request is subsequently ignored.

1 No requests are ignored.

11–7

—

Reserved

Table 16-46. PCI Bus Function Register Field Descriptions (continued)

Bits

Name

Description

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