MPC8540 datasheet(871/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-49

16.3.2.18 PCI Bus Maximum Latency (MAX_LAT) Register

Figure 16-47. PCI Bus Maximum Latency Register

16.3.2.19 PCI Bus Function Register (PBFR)

The 2-byte PCI bus function register is used to determine how different features of the PCI

interface are configured. This register is at PCI configuration space at offset 0x44.

Figure 16-48. PCI Bus Function Register

MAXLAT

Reset

0000_0000

Offset

0x3F

Table 16-45. PCI Bus Maximum Latency Register Field Description

Bits

Name

Description

7–0

MAXLAT

Specifies how often the device needs to gain access to the PCI bus (0x00 indicates that this PCI

controller has no major requirements for the settings of latency timers)

ACL

0P64

PAH

Reset

0000_0000_00*0_*00*

*Depends on the state of the reset configuration signals at reset

Offset

0x44

Table 16-46. PCI Bus Function Register Field Descriptions

Bits

Name

Description

15–

—Reserved

ACL

Agent configuration lock. Indicates to an external host whether the local processor is doing internal

configuration and must be explicitly set and cleared by the local processor during this time. ACL is set

during reset if the LA27 (cfg_cpu_boot) input selects the CPU as the configuration owner. This bit is only

meaningful in agent mode.

0 PCI interface allows incoming PCI configuration cycles.

1 PCI interface retries all incoming PCI configuration cycles.

4—

Reserved

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