MPC8540 datasheet(867/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-45

Figure 16-39. 64-Bit Low Memory Base Address Register

Table 16-36. 32-Bit Memory Base Address Register Field Descriptions

Bits

Name

Description

31–1

ADDRES

Indicates the base address at which the inbound memory window resides. The number of upper

bits that the device allows to be writable is selected through the inbound translation windows.

11–4

—

Reserved. The device allows a 4 Kbyte window minimum.

PREF

Prefetchable

2–1

TYPE

Type: 00—Locate anywhere in 32-bit address space.

MSI

Memory Space Indicator.

ADDRESS

Reset

0000_0000_0000_0000

4321

ADDRESS

PRE

TYPE

MSI

Reset

0000_0000_0000_0100

Offset

0x18, 0x20

Table 16-37. 64-Bit Low Memory Base Address Register Field

Descriptions

Bits

Name

Description

31–1

ADDRES

Indicates the base address at which the inbound memory window resides. The number of upper

bits that the device allows to be writable is selected through the inbound translation windows.

11–4

—

Reserved. The device allows a 4 Kbyte window minimum.

PREF

Prefetchable

2–1

TYPE

Type: 10—Locate anywhere in 64-bit address space.

MSI

Memory space indicator

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