MPC8540 datasheet(863/1302 Pages) FREESCALE

863 / 1302 page

Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-41

16.3.2.5 PCI Revision ID Register—Offset 0x08

The PCI Revision ID register is used to identify the revision of the part.

Figure 16-31. PCI Revision ID Register

16.3.2.6 PCI Bus Programming Interface Register—Offset 0x09

Table 16-30 describes the PCI Bus programming interface register (PIR).

Figure 16-32. PCI Bus Programming Interface Register

Master data parity

error detected

Set upon detecting a data parity error. Three conditions must be met for this bit to be set:

• This PCI controller detected a parity error.

• This PCI controller was acting as bus master for the operation in which the error occurred.

• Bit 6 in the PCI bus command register was set.

Fast back-to-back

capable

Hard-wired to 1, indicating that this PCI controller (as a target) is capable of accepting fast

back-to-back transactions

6—

Reserved

66-MHz capable

Read-only bit indicates that this PCI controller is capable of 66 MHz PCI bus operation.

Capabilities List

Hard-wired to 1

3–0

—

Reserved

Revision ID

Reset

revision specific

Offset

0x08

Table 16-29. PCI Revision ID Register Field Descriptions

Bits

Name

Description

7–0

Revision ID

Revision specific

Programming Interface

Reset

0000_000*

*0 = Host, 1 = Agent

Offset

0x09

Table 16-28. PCI Bus Status Register Field Descriptions (continued)

Bits

Name

Description

MPC8540 Datasheet(PDF) 863 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 863 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL