MPC8540 datasheet(861/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-39

Figure 16-29. PCI Bus Command Register

Fast

back-to-

back

SERR

Parity error

response

Memory-write-

and-invalidate

Special

cycles

Bus

master

Memory

space

I/O

space

Reset

0000_0000_0000_0*00

*0 = Agent, 1 = Host

Offset

0x04

Table 16-27. PCI Bus Command Register Field Descriptions

Bits

Name

Description

15–1

—

Reserved

9Fast

back-to-back

Hard-wired to 0, indicating that this PCI controller (as a master) does not run fast back-to-back

transactions

SERR

Controls the PCI_SERR driver of this PCI controller. This bit (and bit 6) must be set to report

address parity errors.

0 Disables the PCI_SERR driver

1 Enables the PCI_SERR driver

7—

Reserved

Parity error

response

Controls whether this PCI controller responds to parity errors.

0 Parity errors are ignored and normal operation continues.

1 Parity errors cause the appropriate bit in the PCI status register to be set. However, note

that errors are reported based on the values set in the PCI error enable and detection

registers.

5—

Reserved

Memory-write

and-invalidate

Hard-wired to 0, indicating that this PCI controller, acting as a master, can not generate the

memory-write-and-invalidate command

Special-cycle

Hard-wired to 0, indicating that this PCI controller (as a target) ignores all special-cycle

commands

Bus master

Indicates whether this PCI controller is configured as a master. This indicates the setting of the

host/agent configuration input (LWE2) at power-on reset.

0 Disables the ability to generate PCI accesses

1 Enables this PCI controller to behave as a PCI bus master (Host)

Note that the Bus master bit in the MPC8540’s PCI bus command register must be set before

any outbound configuration access is attempted.

Memory

space

Controls whether this PCI controller (as a target) responds to memory accesses.

0 This PCI controller does not respond to PCI memory space accesses.

1 This PCI controller (as a target) responds to PCI memory space accesses.

I/O space

Hard-wired to 0, indicating that this PCI controller (as a target) does not respond to PCI I/O

space accesses

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