MPC8540 datasheet(865/1302 Pages) FREESCALE

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Memory Map/Register Definitions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-43

16.3.2.9 PCI Bus Cache Line Size Register—Offset 0x0C

Table 16-33 describes the PCI bus cache line size register (PCLSR).

Figure 16-35. PCI Bus Cache Line Size Register (PCLSR)

16.3.2.10 PCI Bus Latency Timer Register—0x0D

Table 16-34 describes the PCI latency timer register (PLTR).

Figure 16-36. PCI Bus Latency Timer Register

16.3.2.11 PCI Base Address Registers

A PCI base address register points to the beginnings of each address range to which the device

responds by assertingþ PCI_DEVSEL. The base address register (BAR) at offset 0x10 is a fixed

Cache Line Size

Reset

0000_0000 (PCI); 0000_1000 (PCI-X)

Offset

0x0C

Table 16-33. PCI Bus Cache Line Size Register (PCLSR) Field Descriptions

Bits

Name

Description

7–0

Cache

Line

Size

Represents the cache line size of the processor in terms of 32-bit words (eight 32-bit words = 32 bytes).

PCLSR is read-write; however, for PCI operation, an attempt to program this register to any value other

than 0x8 results in clearing it. For PCI-X operation, this register is hardwired to 0x8.

Latency Timer

Reset

0000_0000

Offset

0x0D

Table 16-34. PCI Bus Latency Timer Register Field Descriptions

Bit

Name

Description

7–3

Latency Timer

The maximum number of PCI clocks that the device, when mastering a transaction, holds the bus

after PCI bus grant has been negated. The value is in PCI clocks. The PCI 2.2 specification gives

rules by which the PCI bus interface unit completes transactions when the timer has expired.

2–0

Latency Timer

Read-only bits. The minimum latency timer value when set is 8 PCI clocks.

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