MPC8540 datasheet(870/1302 Pages) FREESCALE

870 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-48

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.3.2.16 PCI Bus Interrupt Pin Register

The MPC8540 does not generate specific PCI_INTA, PCI_INTB, etc. outputs, nor does this device

respond to INTACK or special cycle commands on the PCI/X interfaces. The MPC8540 does have

12 general purpose interrupt request lines (IRQ[0:11]) and an interrupt output, IRQ_OUT (active

low, level sensitive), to which all external and most internal interrupt sources (including PCI/X)

can be routed.

Figure 16-45. PCI Bus Interrupt Pin Register

16.3.2.17 PCI Bus Minimum Grant (MIN_GNT) Register

Figure 16-46. PCI Bus Minimum Grant Register

Table 16-42. PCI Bus Interrupt Line Register Field Description

Bits

Name

Description

7–0

Interrupt Line

This register is used to communicate interrupt line routing information (hard-wired to zero).

Interrupt Pin

Reset

0000_0000

Offset

0x3D

Table 16-43. PCI Bus Interrupt Pin Register Field Description

Bits

Name

Description

7–0

Interrupt Pin

No PCI_INT pin selected

RMIN_GNT

Reset

0000_0000

Offset

0x3E

Table 16-44. PCI Bus Minimum Grant Register Field Description

Bits

Name

Description

7–0

MIN_GNT

Specifies the length of the device’s burst period (0x00 indicates that this PCI controller has no

major requirements for the settings of latency timers)

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