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MPC8540 Datasheet(PDF) 873 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 873 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definitions
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
16-51
16.3.2.21 PCI-X Next Capabilities ID Register—0x60
This register is an additional standard register specified by the PCI-X Addendum to the PCI Local
Bus Specification.
Figure 16-50. PCI-X Next Capabilities ID Register
16.3.2.22 PCI-X Capability Pointer Register—0x61
The PCI-X next capabilities pointer register is an additional standard register specified by the
PCI-X Addendum to the PCI Local Bus Specification. This register identifies additional
functionality supported by the device. The definition of each bit is given in Table 16-49.
Figure 16-51. PCI-X Capability Pointer Register
6–2
PBMP
PCI bus master priorities. Determines arbitration priority given to different masters on the PCI bus. Bit 6
corresponds to the priority of the master sourcing PCI_REQ0; bit 2 corresponds to the priority of the
master sourcing PCI_REQ4.
0Master n is low priority.
1Master n is high priority.
1—
Reserved
0
DP
Device priority. Determines this device’s arbitration priority.
0 Device is low priority.
1 Device is high priority.
7
0
R
Capabilities ID
W
Reset
0000_0111
Offset
0x60
Table 16-48. PCI-X Next Capabilities ID Register Field Descriptions
Bits
Name
Description
7–0
Capabilities ID
This register identifies this item in the capabilities list as a PCI-X device having PCI-X registers.
7
0
R
Capability Pointer
W
Reset
0000_0000
Offset
0x61
Table 16-47. PCI Bus Arbiter Configuration Register Field Descriptions (continued)
Bits
Name
Description



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