MPC8540 datasheet(875/1302 Pages) FREESCALE

875 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-53

Figure 16-53. PCI-X Status Register

16.4 Functional Description

This section describes the functionality of the PCI/X interface.

16.4.1 PCI/X Bus Arbitration

PCI/X bus arbitration is access-based. Bus masters must arbitrate for each access performed on the

bus. The PCI/X bus uses a central arbitration scheme where each master has a unique request

RSM

DMCRS

DMOST

DMRBC

USC

SCD

SBD

Reset

0001_0001_1000_001*

*0 = 32-bit bus, 1 = 64-bit bus

DBN

DDN

DFN

Reset

1111_1111_1111_1010

Offset

0x64

Table 16-51. PCI-X Status Register Field Descriptions

Bits

Name

Description

31–30

—

Reserved

RSM

Receive split completion error message (write-1-to-clear)

28–26

DMCRS

Designed maximum cumulative read size (16 Kbytes)

25–23

DMOST

Designed maximum outstanding split transactions (4 outstanding)

22–21

DMRBC

Designed maximum memory read byte count (128 Bytes)

Device complexity (simple device, can retry writes)

USC

Unexpected split completion (write-1-to-clear)

SCD

Split completion discarded (write-1-to-clear)

133-MHz capability

SBD

64-bit device

15–8

DBN

Bus number (used for diagnostic purposes)

7–3

DDN

Device number (used for diagnostic purposes)

2–0

DFN

Function number (used for diagnostic purposes)

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