MPC8540 datasheet(878/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-56

Freescale Semiconductor

PCI/PCI-X Bus Interface

16.4.1.2 PCI/X Bus Parking

When no device is using or requesting the bus, the PCI/X arbiter grants the bus to a selected device.

This is known as parking the bus on the selected device. The selected device is required to drive

the PCI_AD[31:0], PCI_C/BE[0:3], and the PCI/X parity signals to a stable value, preventing

these signals from floating.

The parking mode parameter (PBACR[PM]) determines which device the arbiter selects for

parking the PCI/X bus. If PBACR[PM] = 0 (or if the bus is not idle), then the bus is parked on the

last master to use the bus. If the bus is idle and PBACR[PM] = 1, the bus is parked on the

MPC8540.

16.4.1.3 Broken Master Lock-Out (PCI only)

The PCI bus arbiter on the MPC8540 has a feature that allows it to lock out any masters that are

broken or ill-behaved. The broken master feature is controlled by programming bit 12 of the PCI

bus arbitration control register (0 = enabled, 1 = disabled). Note that the PCI-X bus arbiter does

not support the broken master lockout function.

When the broken master feature is enabled, a granted device that does not assert PCI_FRAME

within 16 PCI clock cycles after the bus is idle, has its grant removed and subsequent requests are

ignored until its REQ is negated for at least one clock cycle. This prevents ill-behaved masters

from monopolizing the bus. When the broken master feature is disabled, a device that requests the

bus and receives a grant never loses its grant until and unless it begins a transaction or negates its

REQ signal. Note that disabling the broken master feature is not recommended.

16.4.1.4 Power-Saving Modes and the PCI Arbiter

In the sleep power-saving mode, the clock signal driving SYSCLK can be disabled. If the clock is

disabled, arbitration logic cannot perform its function. System programmers must park the bus

with a device that can sustain the PCI_AD[31:0], PCI_C/BE[3:0], and parity signals prior to

disabling the SYSCLK signal. If the bus is parked on the MPC8540 when its clocks are stopped,

the MPC8540 sustains the PCI_AD[31:0], PCI_C/BE[3:0], and parity signals in their prior states.

In this situation, the only way for another agent to use the PCI bus is by waking the MPC8540. In

the doze or nap power-saving modes, the arbiter continues to operate allowing other PCI devices

to run transactions.

16.4.2 PCI Bus Protocol

This section provides a general description of the PCI bus protocol. Specific PCI bus transactions

are described in Section 16.4.2.7, “PCI Bus Transactions.” Refer to Figure 16-55, Figure 16-56,

Figure 16-57, and Figure 16-58 for examples of the transfer-control mechanisms described in this

section.

MPC8540 Datasheet(PDF) 878 Page - Freescale Semiconductor, Inc