MPC8540 datasheet(880/1302 Pages) FREESCALE

880 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-58

Freescale Semiconductor

PCI/PCI-X Bus Interface

Table 16-52. PCI Bus Commands

PCI_C/

BE[3:0]

PCI Bus

Command

MPC8540

Supports as

an Initiator

MPC8540

Supports

as a Target

Definition

0000

Interrupt-

acknowledge

Yes

A read (implicitly addressing the system interrupt controller).

Only one device on the PCI bus should respond to this

command; others ignore it. See Section 16.4.2.12.1,

“Interrupt-Acknowledge Transactions,” for more information.

0001

Special cycle

Yes

Provides a way to broadcast select messages to all devices on

the PCI bus. See Section 16.4.2.12.2, “Special-Cycle

Transactions,” for more information.

0010

I/O-read

Yes

Accesses agents mapped into the PCI I/O space.

0011

I/O-write

Yes

Accesses agents mapped into the PCI I/O space.

0100

Reserved1

1 Reserved command encodings are reserved for future use. The MPC8540 does not respond to these commands.

—

0101

Reserved1

—

0110

Memory-read

Yes

Accesses either local memory or agents mapped into PCI

memory space, depending on the address. When a PCI

master issues this command to local memory, the MPC8540

(the target) fetches data from the requested address to the end

of the cache line (32 bytes) from local memory, even though all

of the data may not be requested by (or sent to) the initiator.

0111

Memory-write

Yes

Accesses either local memory or agents mapped into PCI

memory space, depending on the address.

1000

Reserved1

—

1001

Reserved1

—

1010

Configuration-

read

Yes

Agent mode

only

Access the 256-byte configuration space of a PCI agent. A

specific agent is selected when its IDSEL signal is asserted

during the address phase. See Section 16.4.2.11,

“Configuration Cycles,” for details.

1011

Configuration-

write

Yes

Agent mode

only

1100

Memory-read-

multiple

Yes

Similar to the memory-read command, but also causes a

prefetch of the next cache line (32 bytes).

1101

Dual-address-

cycle

Yes

Used to transfer a 64-bit address (in two 32-bit address cycles)

to 64-bit addressable devices.

1110

Memory-read-

line

Yes

Indicates that an initiator is requesting the transfer of an entire

cache line. This occurs only when the processor is performing

a burst read. Note that these processors perform burst reads

only when the appropriate cache is enabled and the

transaction is not cache-inhibited.

1111

Memory-write-

and-invalidate

Yes

Indicates that an initiator is transferring an entire cache line; if

this data is in any cacheable memory, that cache line needs to

be invalidated.

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