MPC8540 datasheet(884/1302 Pages) FREESCALE

884 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-62

Freescale Semiconductor

PCI/PCI-X Bus Interface

similar for the memory and I/O spaces, so they are described as generic read transactions and

generic write transactions.

The timing diagrams in this section show the relationship of significant signals involved in bus

transactions. When a signal is drawn as a solid line, it is actively being driven by the current master

or target. When a signal is drawn as a dashed line, no agent is actively driving it. High-impedance

signals are indicated to have indeterminate values when the dashed line is between the two rails.

The terms ‘edge’ and ‘clock edge’ always refer to the rising edge of the clock; ‘asserted’ and

‘negated’ always refer to the globally visible state of the signal on the clock edge, and not to signal

transitions. ‘

’ represents a turnaround cycle in the timing diagrams.

16.4.2.7.1 PCI Read Transactions

This section describes PCI single-beat read transactions and PCI burst read transactions.

A read transaction starts with the address phase, occurring when an initiator asserts PCI_FRAME.

During the address phase, PCI_AD[63:0] contains a valid address and PCI_C/BE[7:0] contains a

valid bus command.

The first data phase of a read transaction requires a turnaround cycle. This allows the transition

from the initiator driving PCI_AD[63:0] as address signals to the target driving PCI_AD[63:0] as

data signals. The turnaround cycle is enforced by the target with the TRDY signal. The target

provides valid data at the earliest one cycle after the turnaround cycle. The target must drive the

PCI_AD[63:0] signals when PCI_DEVSEL is asserted.

During the data phase, the PCI_C/BE[7:0] signals indicate which byte lanes are involved in the

current data phase. A data phase may consist of a data transfer and wait cycles. The

PCI_C/BE[7:0] signals remain actively driven for both reads and writes from the first clock of the

data phase through the end of the transaction.

A data phase completes when data is transferred, which occurs when both PCI_IRDY and

PCI_TRDY are asserted on the same clock edge. When either PCI_IRDY or PCI_TRDY is

negated, a wait cycle is inserted and no data is transferred. The initiator indicates the last data

phase by negating PCI_FRAME when PCI_IRDY is asserted. The transaction is considered

complete when data is transferred in the last data phase.

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