MPC8540 datasheet(887/1302 Pages) FREESCALE

887 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-65

transactions are concluded when PCI_FRAME and PCI_IRDY are both negated, indicating the

bus is idle.

16.4.2.8.1 Master-Initiated Termination

Normally, a master initiates termination by negating PCI_FRAME and asserting PCI_IRDY. This

indicates to the target that the final data phase is in progress. The final data transfer occurs when

both PCI_TRDY and PCI_IRDY are asserted. The transaction is considered complete when data

is transferred in the last data phase. After the final data phase, both PCI_FRAME and PCI_IRDY

are negated (the bus becomes idle).

There are three types of master-initiated termination:

•

Completion—Refers to termination when the initiator has concluded its intended

transaction. This is the most common reason for termination.

•

Timeout—Refers to termination when the initiator loses its bus grant (GNTn is negated),

and its internal latency timer has expired. The intended transaction is not necessarily

concluded.

•

Master-abort—An abnormal case of master-initiated termination. If no device (including

the subtractive decoding agent) asserts PCI_DEVSEL to claim a transaction, the initiator

terminates the transaction with a master-abort. For a master-abort termination, the initiator

negates PCI_FRAME and then negates PCI_IRDY on the next clock. If a transaction is

terminated by master-abort (except for a special-cycle command), the received

master-abort bit (bit 13) of the PCI bus status register is set.

As an initiator, if the MPC8540 does not detect the assertion of PCI_DEVSEL within four clock

cycles following the address phase (five clock cycles after asserting PCI_FRAME), it terminates

the transaction with a master-abort.

16.4.2.8.2 Target-Initiated Termination

By asserting PCI_STOP, a target may request that the initiator terminate the current transaction.

Once asserted, the target holds PCI_STOP asserted until the initiator negates PCI_FRAME. Data

may or may not be transferred during the request for termination. If PCI_TRDY and PCI_IRDY

are asserted during the assertion of PCI_STOP, data is transferred. However, if PCI_TRDY is

negated when PCI_STOP is asserted, it indicates that the target will not transfer any more data;

therefore, the initiator does not wait for a final data transfer as it would in a completion

termination.

When a transaction is terminated by PCI_STOP, the initiator must negate its REQn signal for a

minimum of two PCI clock cycles, (one corresponding to when the bus goes to the idle state

(PCI_FRAME and PCI_IRDY negated)). If the initiator intends to complete the transaction, it can

reassert its REQn immediately following the two clock cycles. If the initiator does not intend to

complete the transaction, it can assert REQn whenever it needs to use the PCI bus again.

MPC8540 Datasheet(PDF) 887 Page - Freescale Semiconductor, Inc

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