MPC8540 datasheet(890/1302 Pages) FREESCALE

890 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-68

Freescale Semiconductor

PCI/PCI-X Bus Interface

The three disconnect terminations are unique in the data transferred at the end of the transaction.

For disconnect A, the initiator is negating PCI_IRDY when the target asserts PCI_STOP and data

is transferred only at the end of the current data phase. For disconnect B, the target negates

PCI_TRDY one clock after it asserts PCI_STOP, indicating that the target can accept the current

data, but no more data can be transferred. For disconnect-without-data, the target asserts

PCI_STOP when PCI_TRDY is negated indicating that the target cannot accept any more data.

16.4.2.9 Fast Back-to-Back Transactions

The PCI bus allows fast back-to-back transactions by the same master. During a fast back-to-back

transaction, the initiator starts the next transaction immediately without an idle state. The last data

phase completes when PCI_FRAME is negated, and PCI_IRDY and PCI_TRDY are asserted. The

current master starts another transaction in the clock cycle immediately following the last data

transfer for the previous transaction.

Fast back-to-back transactions must avoid contention on the PCI_TRDY, PCI_DEVSEL,

PCI_PERR, and PCI_STOP signals. There are two types of fast back-to-back transactions—those

that access the same target and those that access multiple targets sequentially. The first type places

the burden of avoiding contention on the initiator; the second type places the burden of avoiding

contention on all potential targets.

As an initiator, the MPC8540 does not perform any fast back-to-back transactions. As a target, the

MPC8540 supports both types of fast back-to-back transactions.

During fast back-to-back transactions, the MPC8540 monitors the bus states to determine if it is

the target of a transaction. If the previous transaction was not directed to the MPC8540 and the

current transaction is directed at the MPC8540, it delays the assertion of PCI_DEVSEL (as well

as PCI_TRDY, PCI_STOP, and PCI_PERR) for one clock cycle to allow the other target to stop

driving the bus.

16.4.2.10 Dual Address Cycles

The MPC8540 supports dual address cycle (DAC) commands (64-bit addressing on PCI bus) as

both an initiator and a target. DACs are different from single address cycles (SACs) in that the

address phase takes two PCI beats instead of one PCI beat to transfer (64-bit vs. 32-bit addressing).

Only PCI memory commands can use DAC cycles; I/O, configuration, interrupt acknowledge, and

special cycle command cannot use DAC cycles. The MPC8540 block supports single-beat and

burst DAC transactions.

For the case of the local processor, DAC generation depends on the setting of the POTEARx. If

the POTEARx are programmed with nonzero values and a transaction from the local processor

core hits in one of the outbound windows, a DAC transaction is generated on the PCI bus with the

translated lower 32-bit addresses. Refer to Section 16.3.1.2, “PCI/X ATMU Outbound Registers,”

for more information.

MPC8540 Datasheet(PDF) 890 Page - Freescale Semiconductor, Inc