MPC8540 datasheet(893/1302 Pages) FREESCALE

893 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-71

16.4.2.11.1 PCI Configuration Space Header

Figure 16-65 shows the predefined header for all PCI devices.

Figure 16-65. Standard PCI Configuration Header

The first 64 bytes of the 256-byte configuration space consists of a predefined header that every

PCI device must support. The first 16 bytes of the predefined header are defined the same for all

PCI devices; the remaining 48 bytes of the header may have differing layouts depending on the

function of the device. Most PCI devices use the configuration header layout shown in

Figure 16-65. The rest of the 256-byte configuration space is device-specific. The PCI header

specific to the MPC8540 is described in Section 16.3.2, “PCI/X Configuration Header.”

Table 16-54 summarizes the configuration header registers. Detailed descriptions of these

registers are provided in the PCI Local Bus Specification, Rev. 2.2.

Device ID

Vendor ID

Status

Command

Class Code

Revision ID

BIST

Latency Timer

Header Type

Cache Line Size

Max_Lat

Interrupt Pin

Min_Gnt

Interrupt Line

0x00

0x04

0x08

0x3C

Address

Offset

0x2C

0x14

0x18

0x1C

0x20

0x24

0x28

0x30

0x34

0x38

0x10

0x0C

Expansion ROM Base Address

Reserved

Base Address Registers

Subsystem ID

Subsystem Vendor ID

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