MPC8540 datasheet(896/1302 Pages) FREESCALE

896 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

16-74

Freescale Semiconductor

PCI/PCI-X Bus Interface

Code sequence:

stw r0, 0 (r1)

// Update PCI CFG_ADDR register to point to

//register offset 0x14 of device 1.

stwbrx r3, 0 (r2)

Results:

Address CCSRBAR + 0x0_8000 contains 0x8000_0814

Example: Configuration sequence, 2-byte data write to PCI register at address offset 0x1C of

Device 1 on PCI/X bus 0.

Initial values:

r0 contains 0x8000_081C

r1 contains CCSRBAR + 0x0_8000

r2 contains CCSRBAR + 0x0_8004

r3 contains 0xDDCC_BBAA

Code sequence:

stw r0, 0 (r1)

sthbrx r3, 0 (r2)

Results:

Address CCSRBAR + 0x0_8000 contains 0x8000_081C

16.4.2.11.3 PCI Configuration in Agent and Agent Lock Modes

In general, agents should not access the configuration space of other external PCI devices.

Configuration of agents is a function usually reserved for the host. When the MPC8540 is in agent

mode, it responds to remote host-generated PCI/X configuration cycles. This occurs when a

configuration command is decoded along with the IDSEL input signal being asserted. When the

MPC8540 is in agent lock mode, it retries all externally-generated PCI/X configuration cycles

until the ACL bit in the PCI bus function register (0x44) is set. See Section 16.5.1, “Power-On

Reset Configuration Modes,” for more information.

In either agent or agent lock mode, access to the internal PCI/X configuration header by the

processor core is handled as described in Section 16.4.2.11.2, “Accessing the PCI Configuration

Space in Host Mode,” using device = 0 and bus = 0 in PCI CFG_ADDR to indicate the internal

PCI/X header.

16.4.2.11.4 PCI Type 0 Configuration Translation

Figure 16-66 shows the PCI type 0 translation function performed on the contents of the PCI

CFG_ADDR register to the PCI_AD[31:0] signals on the PCI bus during the address phase of the

configuration cycle.

MPC8540 Datasheet(PDF) 896 Page - Freescale Semiconductor, Inc