MPC8540 datasheet(899/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

16-77

devices on the bus should ignore the interrupt-acknowledge command. As stated previously, the

MPC8540 PIC unit does not respond to PCI interrupt-acknowledge commands.

During the data phase, the responding device returns the interrupt vector on PCI_AD[63:0] when

PCI_TRDY is asserted. The size of the interrupt vector returned is indicated by the value driven

on PCI_C/BE[7:0].

The MPC8540 also can generate PCI interrupt-acknowledge transactions directly. Reads from PCI

INT_ACK at offset 0x0_8008 generate PCI interrupt-acknowledge transactions. Note that

processor writes to these addresses do nothing.

16.4.2.12.2Special-Cycle Transactions

The special-cycle command provides a mechanism to broadcast select messages to all devices on

the PCI bus. The special-cycle command contains no explicit destination address but is broadcast

to all PCI agents.

When the MPC8540 detects a write to PCI CFG_DATA, it checks the enable flag and the device

number in PCI CFG_ADDR. If the enable bit is set, the bus number corresponds to the local PCI

bus (bus number = 0x00), the device number is all ones (0b1_1111), the function number is all ones

(0b111), and the register number is zero (0b00_0000), then the MPC8540 performs a special-cycle

transaction on the local PCI bus. If the bus number indicates a nonlocal PCI bus, the MPC8540

performs a type 1 configuration cycle translation, similar to other configuration cycles for which

the bus number does not match.

Aside from the special-cycle command (PCI_C/BE[3:0] = 0b0001) the address phase contains no

other valid information. Although there is no explicit address, PCI_AD[63:0] are driven to a stable

state, and parity is generated. During the data phase, PCI_AD[63:0] contain the special-cycle

message and an optional data field. The special-cycle message is encoded on the

16 least-significant bits (PCI_AD[15:0]); the optional data field is encoded on the most-significant

16 lines (PCI_AD[31:16]). The special-cycle message encodings are assigned by the PCI SIG

steering committee. The current list of defined encodings are provided in Table 16-56.

Note that the MPC8540 does not automatically issue a special-cycle message when it enters any

of its power-saving modes. It is the responsibility of software to issue the appropriate special-cycle

message, if needed.

Table 16-56. Special-Cycle Message Encodings

PCI_AD[15:0]

Message

0x0000

SHUTDOWN

0x0001

HALT

0x0002

x86 architecture-specific

0x0003–0xFFFF

—

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